DeutschesFachbuch.de : Digital VLSI Systems Design A Design Manual for Implementation of Projects on FPGAs and ASICs using Verilog Von Seetharaman Ramachandran

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Contents
Prefacexiii
Chapter 1 Introduction to Digital VLSI Systems Design 3
1.1 Evolution of VLSI Systems 4
1.2 Applications of VLSI Systems 5
1.3 Processor Based Systems 7
1.4 Embedded Systems 8
1.5 FPGA Based Systems 9
1.5.1 FPGA Based Design: Video Compression as an Example 9
1.6 Digital System Design Using FPGAs 13
1.6.1 Spartan-3 FPGAs 14
1.7 Reconfigurable Systems Using FPGAs 24
1.8 Scope of the Book 25
1.8.1 Approach 25
Chapter 2 Review of Digital Systems Design 33
2.1 Numbering Systems 33
2.2 Twos Complement Addition/Subtraction 35
2.3 Codes 37
2.3.1 Binary and BCD Codes 37
2.3.2 Gray Code 39
2.3.3 ASCII Code 40
2.3.4 Error Detection Code 41
2.4 Boolean Algebra 43
2.5 Boolean Functions Using Minterms and Maxterms 44
2.6 Logic Gates 46
2.7 The Karnaugh MAP Method of Optimization of Logic Circuits 47
2.8 Combination Circuits 50
2.8.1 Multiplexers 50
2.8.2 Demultiplexers 51
2.8.3 Decoders 52
2.8.4 Magnitude Comparator 53
2.8.5 Adder/Subtractor Circuits 55
2.8.6 SSI and MSI Components 58
2.9 Arithmetic Logic Unit 58
2.10 Programmable Logic Devices 59
2.10.1 Read-Only Memory 61
2.10.2 Programmable Logic Array (PLA)62
2.10.3 Programmable Array Logic (PAL)63
2.11 Sequential Circuits 64
2.12 Random Access Memory (RAM)72
2.13 Clock Parameters and Skew 73
2.14 Setup, Hold, and Propagation Delay Times in a Register 74
2.14.1 Estimation of Maximum Clock Frequency for a Sequential Circuit 75
2.14.2 Metastability of Flip-flops 76
2.15 Digital System Design Using SSI/MSI Components 77
2.15.1 Two-bit Binary Counter Using JK Flip-flops 77
2.15.2 Design of a Three-bit Counter Using T and D Flip-flops 80
2.15.3 Controlled Three-bit Binary Counter Using ROM and Registers 83
2.16 Algorithmic State Machine 85
2.17 Digital System Design Using ASM Chart and PAL 87
2.17.1 Single Puiser Using ASM Chart 87
2.17.2 Design of a Vending Machine Using PAL 90
Chapter 3 Design of Combinational and Sequential Circuits Using Verilog 107
2.17.4 Introduction to Hardware Design Language 107
2.17.5 Design of Combinational Circuits 109
3.2.1 Realization of Basic Gates 110
3.2.2 Realization of Majority Logic and Concatenation 111
3.2.3 Shift Operations 112
3.2.4 Realization of Multiplexers 113
3.2.5 Realization of a Demultiplexer 116
3.2.6 Verilog Modeling of a Full Adder 118
3.2.7 Realization of a Magnitude Comparator 120
3.2.8 A Design Example Using an Adder and a Magnitude Comparator 121
3.3 Verilog Modeling of Sequential Circuits 123
3.3.1 Realization of aD Flip-flop 123
3.3.2 Realization of Registers 124
3.3.3 Realization of a Counter 127
3.3.4 Realization of a Non-retriggerable Monoshot 128
3.3.5 Verilog Coding of a Shift Register 130
3.3.6 Realization of a Parallel to Serial Converter 132
3.3.7 Realization of a Model State Machine 134
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Index A A to D converters, 108
ABS, 660
AC coefficients, 432
Actel, 23
adder, 5
AGP, 489
Alarm Annunciator, 664
Algorithmic State Machine (ASM), 33, 87
algorithms, 11, 28, 417, 675
Altera, 26, 280
always block, 112
application specific instruction processors, 8
architecture, 28, 473, 487, 599, 689
Arithmetic Logic Unit, 60
ASCII Code, 40
ASIC, 8
ASM chart, 487
assemblers, 9 assign statements, 110
Auto-focus cameras, 662
automatic pruning level control
algorithm, 435
Automatic Quality Control, 431
automatic transmission, 660
automotive, 8, 659, 660
avionic, 7, 659
Avnet, 555
Bback annotation, 29, 299
bandwidth, 3
behavioral, 109, 119
binary coded decimal (BCD), 38
binary counter, 79
binary numbers, 34
Biometrics, 672
bit stream, 13, 15, 16, 305, 328, 329, 336, 432, 589
bit-rate, 12
bits per pixel, 452
block matching algorithm, 417, 453
Block RAMs, 17
Bluetooth, 6
Bottom-up design, 223
Boundary Scan, 19
bus arbitration, 487
Ccase statement, 115
cell phone, 6, 671
cellular communications, 3 characteristic equation, 67
characteristics table, 71
CLB, 18
clock speed, 299
Clock transition, 68
coarse grain configuration, 27
Coding Organization, 139
combination, 51
comparator, 5
Compilation, 15, 227, 255
compilation errors, 282
compilers, 9
complex algorithm, 372
complex instruction set computers, 8
compression, 10, 450
computationally intensive, 371
computer aided design, 3
CAD, 3
Concatenation, 111
concurrent processing, 337
configuration, 19, 297
constant bit rate, 431
constraints, 299
constraints file, 296
control system, 659
controller, 359, 362
controller design, 352
counter, 60, 80, 82, 127
critical paths, 261
DD flip-flop, 123
D to A converters, 108
data acquisition systems, 8 data flow, 18, 109
data flow structure, 119
data processing systems, 8
DC coefficient, 432
DCT coefficients, 421, 432
DCTQ, 28, 473, 503
DCTQ algorithm, 419
debounce, 560
decoder, 5, 53
demo set-up, 589
Demodulator for satellite communication, 7, 663
demultiplexer, 5, 53, 116
Design Manager, 295
design methodology, 14, 29, 222
development cycle, 219
development cycle time, 659
development system, 16
Digilent Inc., 555
digital cable TV, 13
Digital cinema systems, 665
Digital Clock Manager, 18
digital signal processors, 8
DSP, 8
Digital System Design, 79
disadvantages in schematic design, 108
Discrete Cosine Transform (DCT), 12, 417, 418, 487
Discrete Wavelet Transforms, 12
Distributed RAM, 20
downloading, 16, 592, 652
Dual Address ROM Design, 325
dual RAM, 336, 337, 346, 349, 351
dual-port, 18
duty cycle, 75
EEDIF, 221, 256, 272
EDIF file, 267
Electro cardiograph, 7 electronic design automation, 3
EDA, 3
Electrostatic precipitator (EP) controller, 664, 676
embedded systems, 4, 9, 660, 667, 673
emulators, 9 encoder, 5
Encryption/decryption, 7, 663
EPLD, 280
EPROM, 19
EPS, 660
Error correction codes, 663
error detection and correction techniques, 14
Error Detection Code, 42
even parity, 43
excitation tables, 71
external RAM, 352, 358, 361
Ffall time, 74 falling edge, 65
fast one-at-a-time step search (FOSS) algorithm, 453
FFT, 432
Field programable gate arrays, 4
FPGA, 4
fine grain configuration, 27
finite state machine (FSM), 135
Fire wire, 488
fixed pruning level control, 421 fixed-point arithmetic, 371
Flash PROM, 19
Flash RAM, 557
Flight simulator, 662
flip-flop, 33
- D, 66
- JK, 66
- RS, 66
- T, 66 floating point arithmetic, 371
floor plan, 299
Floor Planner, 295
FOSS motion estimation processor, 479
FPGA based Systems, 10
FPGA boards, 555
FPGA/ASIC Implementations, 659
frequency of operation, 260
FSM Viewer, 268 full adder, 57, 118 full reconfiguration, 27 full subtractor, 59
full_case, 271
Ggate count, 15, 329, 365, 413
gates, 33, 47
glitches, 193
Global positioning system, 7, 661
Gray codes, 39
GSM, 6
HH. 261, 11
H. 263, 28
H. 264, 12, 548, 684
H. 264
- codec, 666
half adder, 56
half subtractor, 58
Hamming code, 43
hardware architecture, 15
hardware design language, 10, 107
hardware setup, 649
Hardware/software co-design, 9
HDTV, 11
header information, 689
hexadecimal, 34
high resolution motion pictures, 10
hold time, 75, 76, 194
human visual system, 14
IIEEE standards, 109
image block, 432
implementations, 11
Informtion Technology, 3
IT, 3 injecting errors, 282
Instrument landing system, 7, 662
integrated circuits, 3
IC, 3
intellectual property, 222
Inverse Discrete Cosine Transform (IDCT), 13
Inverse Quantization (IQ), 13
IOB, 18
Ipods, 6
IQIDCT, 28
ISO, 11
ITU, 11
JJPEG, 11
JPEG 2000, 12, 684
JPEG 2000 codec, 666
JTAG, 19
KKarhunen Loeve Transform (KLT), 418
Karnaugh map, 33, 48, 256
LLAN/WAN, 8
large scale integration, 5
LSI, 5 latch, 199, 271
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