DeutschesFachbuch.de : The NeuroProcessor An Integrated Interface to Biological Neural Networks Von Yevgeny Perelman, Ran Ginosar

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Contents
1 Introduction 1
1.1 Overview of the Book 3
2 Recording From Biological Neural Networks 5
2.1 The Neuron 5
2.1.1 The Membrane and Resting Potential 6
2.1.2 Action Potential 7
2.1.3 Excitation Propagation 8
2.2 Interfacing Neurons Electrically 10
2.2.1 Double Layer Capacitance 10
2.2.2 Resistance at the Interface and Charge Transfer 11
2.2.3 Diffusion Resistance Near DC 12
2.2.4 AC Diffusion Resistance 13
2.2.5 Electrode Noise 14
2.3 Neuronal Probes for Extracellular Recording 15
2.3.1 Penetrating Electrodes 16
2.3.2 Cuff Electrodes and Regenerating Sieve Electrodes 17
2.4 Recording from Cultured Neural Networks 17
2.4.1 MEAs on Silicon Substrate 17
2.5 Typical Multi-Electrode Recording Setup 18
2.6 Recorded Signal Information Content 20
3 The Neuroprocessor 23
3.1 Datarate Reduction in Neuronal Interfaces 24
3.2 Neuroprocessor Overview 24
4 Integrated Front-End for Neuronal Recording 27
4.1 Background 27
4.1.1 Blocking the DC Drifts 27
4.2 NPR 01: First Front-End Generation 30
4.3 NPR 02: Analog Front-End With Spike/LFP Separation 31
4.3.1 Splitting Spike and LFP 31
4.3.2 NPR 02: Architecture 32
4.3.3 Input Preamplifier 34
4.3.4 NPR 02: Measurements 35
5 NPR 03: Mixed-Signal Integrated Front-End for Neuronal Recording 39
5.1 Overview 39
5.2 NPR 03: Architecture 40
5.2.1 Chip Communications 41
5.2.2 Instruction Set and Register Access 42
5.3 Host Interface 43
5.4 NPR 03: Channel 44
5.5 Analog-to-Digital Converter 44
5.6 Integrated Preamplifier With DC Blocking 46
5.6.1 Choosing Ci, and Cf 46
5.6.2 Noise Analysis 47
5.6.3 Discussion 51
5.7 NPR 03: Measurements 52
5.8 An NPR 03 -Based Miniature Headstage 53
5.9 A Novel Opamp for The Front-End Preamplifier 58
5.9.1 Noise Analysis 61
5.9.2 Stability 65
5.9.3 Conclusions 67
5.10 Conclusions 67
6 Algorithms for Neuroprocessor Spike Sorting 69
6.1 Introduction 69
6.1.1 Clustering Methods 69
6.1.2 Spike Detection and Alignment 71
6.1.3 Issues in Spike Sorting 71
6.2 Spike Sorting in a Neuroprocessor 72
6.3 Spike Sorting Algorithms 73
6.3.1 PCA Approximations 74
6.3.2 Time Domain Classification 75
6.3.3 Integral Transform 76
6.3.4 Decision Boundaries 77
6.3.5 Validation 77
6.4 Detection and Alignment Algorithms 79
6.4.1 Algorithms Verified 79
6.4.2 Validation Results 80
7 MEA on Chip: In-Vitro Neuronal Interfaces 81
7.1 Prototype Sensor 83
7.1.1 Electrode Design 83
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Index
AAC coupling, 28
action potential, 6, 7
ADC, 39, 44
alignment, 71
amplifier, 14
axon, 6
Bband-splitting, 31
bath, 86
Ccluster, 70
clustering, 69
CMOS multi-electrode array, 94
CMOS multi-electrode chip, 82
computational neuronal interfaces, 3
DDAC, 33, 44
datarate, 23, 24
DC blocking, 27, 29, 31, 39, 46, 85
DC drifts, 27
DC offsets, 33
dielectric layer, 84
differential, 67
digitization, 25
dynamic range, 31
Eelectrode, 10, 88
epoxy, 87
exchange current density, 12
Ffront-end, 30, 31
Hhard decision, 75
headstage, 19, 53
heater, 86
Iin-vitro, 2, 84, 94
in-vivo, 2
input preamplifier, 44, 58
integral transform, 76
Llocal field potential, 27, 31, 32
low-power algorithms, 94
Mmaximum integral transform alignment, 80
maximum projection alignment, 80
measurements, 52
multi-electrode array, 2, 17, 81
multi-electrode chip, 18, 82
Nneuron, 6
neuronal interfacing, 2
neuronal prosthetics, 24
neuroprocessor, 3, 23, 24, 93
neurostimulation, 10
noise, 14, 32, 47, 52, 61
Ooverlapping spikes, 71
PPCA, 73
penetrating electrodes, 16
PSRR, 31
pulse train, 71
Rrecording, 25
refractory period, 8
SSAH, 44
segmented PC A, 74
shape-space, 70
software, 43
soma, 6
space charge layer, 10
spike-detection, 21, 24, 69
spike-sorting, 21, 24, 69
spikes, 20
stability, 65
stimulation, 25
switching noise, 30
Sylgard, 87
synapse, 6
Ttemperature sensor, 86
threshold crossing, 41
threshold detection, 31
threshold-crossing, 71
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